Vista isn't as much garbage as you guys seem to think it is. I have been running it since the week after it came out and haven't had a problem with it besides a minor issue with itunes that Apple is gonna fix in the new Itunes that should be out soon. Vista is actually, in my experience, more stable than XP.
New Computer Blues
- Thread starter DZwart
- Start date
MaidMirawyn
New Member
LOL
Remind me again, Thrain, how many components you had to upgrade...
Remind me again, Thrain, how many components you had to upgrade...
instead of reading the entire thread im kinda interested in what u did have to upgrade cuz im pretty sure my system can run everything just fine, and i can get home premium for $89 through my college
Baron Squirrel
New Member
M$ has a tool you can download to see if your system will support Vista, or at least they did...
my fear is drivers though not if the hardware can handle it
ChickenSoup
Banned
MaidMirawyn
New Member
He posted about it here...and I know that at least a week later he was still having mic problems, though I have no idea if it was drivers or what. Never asked.
I don't know enough about Vista to say good or bad, but I thought Thrain's remark was funny, taken in context. He's very enthusiastic about Vista, though, now that it's running.
DZwart
Legacy of Elijah Officer
AAAAAAAAAAAAAAGGGGGGGGGGGGGGHHHHHHHHHHHHHHHHHHHHH!
I got my replacement RAM from OCZ yesterday and...
It does the exact same thing!!!!!!!!
I've sent messsages to both OCZ (RAM) and ECS (Mobo) asking for suggestions. I'm going to look into the BIOS a little deeper tonight to see if I can find RAM voltage control, but don't remember finding anything before. There appears to be a BIOS update available dated early Feb07, I'll have to look at the label on the box to see what the manufacture date of the mobo was. Anybody have any other thoughts?
At least I can use the new machine with 1GB in it for the weekend, but I want the 2 GB I paid for to work!
Just as a refresher here's the specs:
CPU - Intel Core 2 Duo E6400
RAM - OCZ 2GB
MoBo - ECS P965T-A
I got my replacement RAM from OCZ yesterday and...
It does the exact same thing!!!!!!!!
I've sent messsages to both OCZ (RAM) and ECS (Mobo) asking for suggestions. I'm going to look into the BIOS a little deeper tonight to see if I can find RAM voltage control, but don't remember finding anything before. There appears to be a BIOS update available dated early Feb07, I'll have to look at the label on the box to see what the manufacture date of the mobo was. Anybody have any other thoughts?
At least I can use the new machine with 1GB in it for the weekend, but I want the 2 GB I paid for to work!
Just as a refresher here's the specs:
CPU - Intel Core 2 Duo E6400
RAM - OCZ 2GB
MoBo - ECS P965T-A
Hescominsoon
CGA\TOJ Hosting Manager
JDEC specs only allow for a certain number of banks per slot. i bet the ram is not conforming to standards correctly especially since it works fine with two slots but not 4. Probably more than one bank per slot on the sticks..which is going to cuase problems.
I quote from a blog i read form:
The lesser known things to know about memory
Memory is probably the most misunderstood aspect of PC assembly. To start, the synchronous timing/signaling used is hardly the performance metric. To continue, virtually all vendors promote violation of JEDEC specifications.
DDR JEDEC Spec DIMMs DDR2 JEDEC Spec DIMMs
---- ---------- ----- ---- ---------- -----
200 PC-1600 3 400 PC2-3200 1
266 PC-2100 2 533 PC2-4200 1
333 PC-2700 2 667 PC2-5300 1
400 PC-3200 1 800 PC2-6400 1
Seeing a repeat theme here? Only 1 DIMM per channel for any DDR2 speed as well as PC-3200 DDR400. On any JEDEC compliant DDR memory controller, using more than 1 PC-3200 (DDR-400) DIMM per channel will result in the signaling slowing down to PC-2700 (DDR-333), which people regularly complain about. These are doubled for "Registered/Buffered" DIMMs, but desktop systems rarely offer them (let alone the newer, "Fully Buffered (FB)" DDR2 DIMMs in newer servers/desktops).
Socket-754 (DDR) is a single channel, direct, 184-pin trace from the CPU, so Socket-754 runs into this limitation directly. Socket-939 (DDR) offers two, 184-pin traces from the CPU, so has limits that are double. Socket-940/AM2 offers two DDR2 channels, so it can only support two (2) DIMMs, period, under JEDEC specification (for stability). Despite marketing, Socket-478 (DDR) runs into single channel issues. LGA-775 is dual channel, so it can only support two (2) DIMMs, period, for JEDEC like Socket-940/AM2.
Timing of the DRAM cells in DRAM ICs on a DRAM DIMM is the biggest performance factor, by far.
The first thing to understand about simple, Dynamic Random Access Memory (DRAM) cells, even those on Synchronous DRAM packages, is that they do not have a clock that runs synchronously with the channel. The MHz signaling does not correspond to the actual cell "latency." That is, a 667MHz (PC2-5300) DDR2 SDRAM module does NOT have 1.5ns (1/666,666,667 of a second) timing. In fact, it doesn't mean it has 3.0ns timing (since two bits are transferred per clock) either.
DRAM cells are typically between 20 to 60ns latency (only 16 to 50MHz -- yes sixteen to fifty). That means it takes several cycles when reading to even get the "first bit of data." Synchronous DRAM attempts to mitigate these great latencies by bursting transfer in pages, typically 4K on x86/x86-64 (what Intel calls IA-32/IA-32e) processors.
Writes are virtually synchronous because they are "send and forget." They will move to the SRAM (static RAM) cache of the processor and/or board, and eventually be sent out to memory. No real latency impact. But reads are devastating if they are not in the SRAM cache already, as the great latency difference between the processor/board and its SRAM and the system DRAM adds great delay. A "cache miss" in modern, superscalar microprocessors and their board interconnects causes an exponential performance hit (of typically over a magnitude).
The SPD chip on each DIMM reports to the channel its various CAS, RAD, RP and RAS timings for the synchronous clock rate. For any DIMM product, you will typically see four (4) timings like 2.5-3-3-6 DDR400/PC-3200 or 5-5-5-15 on DDR2-800/PC2-6400 SDRAM modules (which are pretty good timings). Taking in the synchronous timing, you can figure out the CAS, RAD, RP and RAS of the SDRAM module. If you're intersted more on each definition, see the Wikipedia page (I will not go into them here).
A RAS of 6 on DDR400/PC-3200 means 6 cycles at 200MHz DDR = 6 * 5ns = 30ns (33.3MHz equivalent) maximum delay to access a select row of data in a DRAM IC.
A RAS of 15 on DDR2-800/PC2-6400 means 15 cycles at 400MHz DDR = 15 * 2.5ns = 37.5ns (26.6MHz equivalent) maximum delay to access a select row of data in a DRAM IC.
A RAS of 15 on DDR2-667/PC2-5300 means 15 cycles at 333MHz DDR = 15 * 3ns = 45ns (22.2MHz equivalent) maximum delay to access a select row of data in a DRAM IC.
Yes, latency is not the only factor, as increased, synchronous singling means increased Data Transfer Rate (DTR) -- especially since pages are fetched 4K at a time. But if you're reading more than writing, have a smaller CPU cache (not just L2, but also L1 -- remember, AMD processors have 4x the L1 cache of Intel processors -- long story), etc... latency can have a far greater impact than DTR.
This is why even cheap DDR2 memory can be outperformed by quality DDR, resulting in overall system performance even being 10-20% better. Having directly memory channels on the CPU (e.g., AMD Athlon 64/x2/Opteron), let alone a larger L1 cache (which is completely synchronous with the CPU), can make a huge latency difference as well. This is why AMD did not gain much performance in moving from the DDR Socket-939 platform to the DDR2 Socket-940/AM2 platform.
Linkage.
I quote from a blog i read form:
The lesser known things to know about memory
Memory is probably the most misunderstood aspect of PC assembly. To start, the synchronous timing/signaling used is hardly the performance metric. To continue, virtually all vendors promote violation of JEDEC specifications.
- JEDEC banking limits for PC (DDR) and PC2 (DDR2)
- Timing is everything
DDR JEDEC Spec DIMMs DDR2 JEDEC Spec DIMMs
---- ---------- ----- ---- ---------- -----
200 PC-1600 3 400 PC2-3200 1
266 PC-2100 2 533 PC2-4200 1
333 PC-2700 2 667 PC2-5300 1
400 PC-3200 1 800 PC2-6400 1
Seeing a repeat theme here? Only 1 DIMM per channel for any DDR2 speed as well as PC-3200 DDR400. On any JEDEC compliant DDR memory controller, using more than 1 PC-3200 (DDR-400) DIMM per channel will result in the signaling slowing down to PC-2700 (DDR-333), which people regularly complain about. These are doubled for "Registered/Buffered" DIMMs, but desktop systems rarely offer them (let alone the newer, "Fully Buffered (FB)" DDR2 DIMMs in newer servers/desktops).
Socket-754 (DDR) is a single channel, direct, 184-pin trace from the CPU, so Socket-754 runs into this limitation directly. Socket-939 (DDR) offers two, 184-pin traces from the CPU, so has limits that are double. Socket-940/AM2 offers two DDR2 channels, so it can only support two (2) DIMMs, period, under JEDEC specification (for stability). Despite marketing, Socket-478 (DDR) runs into single channel issues. LGA-775 is dual channel, so it can only support two (2) DIMMs, period, for JEDEC like Socket-940/AM2.
Timing of the DRAM cells in DRAM ICs on a DRAM DIMM is the biggest performance factor, by far.
The first thing to understand about simple, Dynamic Random Access Memory (DRAM) cells, even those on Synchronous DRAM packages, is that they do not have a clock that runs synchronously with the channel. The MHz signaling does not correspond to the actual cell "latency." That is, a 667MHz (PC2-5300) DDR2 SDRAM module does NOT have 1.5ns (1/666,666,667 of a second) timing. In fact, it doesn't mean it has 3.0ns timing (since two bits are transferred per clock) either.
DRAM cells are typically between 20 to 60ns latency (only 16 to 50MHz -- yes sixteen to fifty). That means it takes several cycles when reading to even get the "first bit of data." Synchronous DRAM attempts to mitigate these great latencies by bursting transfer in pages, typically 4K on x86/x86-64 (what Intel calls IA-32/IA-32e) processors.
Writes are virtually synchronous because they are "send and forget." They will move to the SRAM (static RAM) cache of the processor and/or board, and eventually be sent out to memory. No real latency impact. But reads are devastating if they are not in the SRAM cache already, as the great latency difference between the processor/board and its SRAM and the system DRAM adds great delay. A "cache miss" in modern, superscalar microprocessors and their board interconnects causes an exponential performance hit (of typically over a magnitude).
The SPD chip on each DIMM reports to the channel its various CAS, RAD, RP and RAS timings for the synchronous clock rate. For any DIMM product, you will typically see four (4) timings like 2.5-3-3-6 DDR400/PC-3200 or 5-5-5-15 on DDR2-800/PC2-6400 SDRAM modules (which are pretty good timings). Taking in the synchronous timing, you can figure out the CAS, RAD, RP and RAS of the SDRAM module. If you're intersted more on each definition, see the Wikipedia page (I will not go into them here).
A RAS of 6 on DDR400/PC-3200 means 6 cycles at 200MHz DDR = 6 * 5ns = 30ns (33.3MHz equivalent) maximum delay to access a select row of data in a DRAM IC.
A RAS of 15 on DDR2-800/PC2-6400 means 15 cycles at 400MHz DDR = 15 * 2.5ns = 37.5ns (26.6MHz equivalent) maximum delay to access a select row of data in a DRAM IC.
A RAS of 15 on DDR2-667/PC2-5300 means 15 cycles at 333MHz DDR = 15 * 3ns = 45ns (22.2MHz equivalent) maximum delay to access a select row of data in a DRAM IC.
Yes, latency is not the only factor, as increased, synchronous singling means increased Data Transfer Rate (DTR) -- especially since pages are fetched 4K at a time. But if you're reading more than writing, have a smaller CPU cache (not just L2, but also L1 -- remember, AMD processors have 4x the L1 cache of Intel processors -- long story), etc... latency can have a far greater impact than DTR.
This is why even cheap DDR2 memory can be outperformed by quality DDR, resulting in overall system performance even being 10-20% better. Having directly memory channels on the CPU (e.g., AMD Athlon 64/x2/Opteron), let alone a larger L1 cache (which is completely synchronous with the CPU), can make a huge latency difference as well. This is why AMD did not gain much performance in moving from the DDR Socket-939 platform to the DDR2 Socket-940/AM2 platform.
Linkage.
Hescominsoon
CGA\TOJ Hosting Manager
so basically if you use more than two dimms you are paying with stability fire and i bet that's what you are hitting.